2005 SOI Conference Committee

Executive Committee

General Chair
MIT Lincoln Lab
Advanced Silicon Technology
244 Wood St.
Group 88, L-302
Lexington, MA  02173

Technical Program Chair

IBM-San Jose Design Center  
5600 Cotttle Road
San Jose, CA

Local Arrangements Chair

Institute of Industrial Science

University of Tokyo

4-6-1 Komaba, Meguro-ku

Tokyo 153-8505, Japan


Treasurer and Registration Chair

LEG Laboratory

Swiss Federal Inst. of Technology

CH-1015 Lausanne, Switzerland




Senior Committee

Rump and Poster Chair


7700 W. Parmer Ln. PL30

Austin, TX 78729-8084



Short Course Chair


One AMD Place

Sunnyvale, CA 94088



Conference Development


Texas Instruments





Advisory Board
  , George Mason University

, Honeywell SSEC

, Freescale Semiconductors



Technical Committee
, University of Michigan

, TSMC Ltd

, IBM Research 

, National Taiwan University

, Honeywell SSEC


, Shin-Etsu Handotai


, American Semiconductor, Inc.


, MIT Lincoln Lab

, Texas Instruments

, Philips Semiconductor


DR. JAMES BURNS received the B.S. degree in physics from the Carnegie Institute of Technology in 1960 and the Ph.D. degree in physics from the University of Vermont in 1975. He worked in semiconductor and magnetic film device design and processing at IBM and CCD design while at Honeywell.  Since 1975 has been a staff member at MIT's Lincoln Laboratory where his principal interests are silicon transistor and process design and the development of analytical techniques to customize IC fabrication to integrated circuit applications. He developed the laboratory's deep sub-micron fully depleted SOI process and is currently working on integrating that SOI technology into a three-dimensional integrated circuit technology. He is a member of the American Physical Society, IEEE, and Tau Beta Pi.

DR. CHRISTOPHE TRETZ received his BSc degree (1991) from the Ecole Nationale Superieure d'Electronique, Electrotechnique, Informatique et Hydraulique de Toulouse (ENSEEIHT), France, and his MS (1992) and PhD in Electrical Engineering (1997) from Columbia University, New York. He joined IBM at the TJ Watson Research Center in Yorktown Heights, NY in 1997 and contributed to the design of several microprocessors for servers and workstations both with bulk and SOI processes. In 2000, he joined Advanced Micro Devices, in the California Microprocessor Division, as a member of the technical staff, and he is contributing to the design of the Hammer microprocessor family, and is establishing design guidelines for microprocessor using SOI technologies. Since mid 2003, he is back with IBM Engineering & Technology Services as a Senior Development Engineer where he is still working on high performance designs using advanced technologies including SOI. Dr. Tretz has authored or coauthored about 25 papers and 3 US patents in the field of circuit design techniques using SOI, circuit optimization and low power design. His current research interests remain in optimizing circuit design for SOI and in improving design choices for SOI.

DR. TOSHIRO HIRAMOTO Toshiro Hiramoto received B.S., M.S., and Ph.D degrees in electronic engineering from the University of Tokyo in 1984, 1986, and 1989, respectively. In 1989, he joined Device Development Center, Hitachi Ltd., Ome, Japan, where he was engaged in the device and circuit design of ultra-fast BiCMOS SRAMs. In 1994, he joined Institute of Industrial Science, University of Tokyo, Japan, as an Associate Professor. He was also an Associate Professor in VLSI Design and Education Center, University of Tokyo, from 1996 to 2002. He has been a Professor in Institute of Industrial Science, University of Tokyo since 2002. His research interests include low power and low voltage design of advanced CMOS devices, SOI MOSFETs, device/circuit cooperation scheme for low power VLSI, quantum effects in nano-scale MOSFETs, and silicon single electron transistors. Dr. Hiramoto is a member of IEEE, IEICE, and Japan Society of Applied Physics. He has been an Elected AdCom Member of IEEE Electron Devices Society since 2001. He served as the Program Chair of Silicon Nanoelectronics Workshop in 1997, 1999, and 2001.

Pierre C. Fazan was born in Lausanne, Switzerland where he obtained his Physics diploma and Ph.D degrees at the Swiss Federal Institute of Technology (EPFL) in 1984 and 1988 respectively. From 1989 to 1997 he worked as process integration engineer then manager at Micron Technology, Boise USA, focusing on DRAM process integration. In 1997 he was named Professor at the Swiss Federal Institute of Technology, Lausanne, EPFL, where he teaches in the field of IC manufacturing.  In 1999 he founded Innovative Silicon Solutions, a consulting company specialized in embedded memory design and integration. In 2002 he co-founded Innovative Silicon, an IP startup developing a new SOI single transistor memory concept. This company was funded in December 2003. He authored or co-authored more than 100 papers and invented or co-invented more than 150 US patents. Dr. Fazan has served as member in program committees of the SOI Conference, IEDM, VLSI Tech. Symp, ISIF, ESSDERC, INFOS and ECS Conferences.

Mario M. Pelella (S'81, M'85, SM'04) received the B.S. and M.S. degrees in electrical engineering from Clarkson University, Potsdam, NY, in 1983 and 1985, respectively. He received the Ph.D. degree in electrical and computer engineering at the University of Florida, Gainesville in 2000.

He joined IBM Microelectronics (General Technology) Division in 1985 where he worked on the device design and modeling of advanced high-speed bipolar transistor technologies and more recently engaged on advanced Silicon-on-Insulator (SOI) CMOS technologies for IBM's, DARPA's and NCCOSC's Low Power Electronics programs. In 1996 he joined the Silicon Technology Innovation and Modeling group at the IBM T.J. Watson Research Center, Yorktown Heigths, NY where he work on improvements to TCAD modeling tools and the analysis of floating-body effects in scaled PD/SOI technologies. He joined the logic technology development group at Advanced Micro Devices in 2000 where he is currently engaged in the development of scaled SOI technologies for the next generation of microprocessors. His research and development interests continue to include the device design, modeling and performance analysis of advanced SOI CMOS technologies, as well as Electrostatic Discharge (ESD) protection devices. He has received over 15 U.S. patents and is an author of over 40-refereed publications.

Dr. Pelella was chairman of the IEEE Electron Device Society Mid Hudson Valley Chapter, 1995-1997, participated on the 1995-1996 and 1996-1997 National Technology Roadmap Committee for Semiconductor Compact Modeling, served on the IEEE International SOI Conference technical program committee during 1996-1998 and now serving on the 2004 senior committee. He was the recipient of the Semiconductor Research Corporation (SRC) outstanding industrial mentor award in 1996. He received a 1983, 1984 TI Fellowship award and a 1998, 1999 IBM Cooperative Fellowship award to pursue his academic research and he was elected senior member of the IEEE in 2004.




Back to SOI Home Page