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Designing circuit using SOI Technologies: Design Tools, Models, Methodology and Design techniques
The theme of this year’s short course is the design of circuit using SOI Technologies: the tools, models, methodology and design techniques required to be successful in this daunting task. The objective of the course is to give to the audience an idea of the design flow, an idea of the issues that should be considered when developing a plan to successfully use SOI for future designs, and an overview of some of the tools available that are SOI specific. Issues begin addressed will include ways to take into account hysteresis into timing analysis and the modifications to traditional approaches of delay acquisition, delay and area minimization while considering floating body effects for gate level tools and various logic styles for transistor level tools, requirements for a good SOI model taking into account the electrical behaviors needed for circuit design, design and layout of various logic and memory circuits. The material presented will be directed towards the principal developments in the SOI field during the past 12 to 18 months and will provide an overview that will enable the attendee to better understand the significance of the papers presented at this year’s conference.

i) Timing Analysis for Large-Scale SOI Designs, Arvind Srinivasan, Circuit Semantics
ii) High level design software, Marty Rana, AltCMOS
iii) SOI Device Modeling for CAD, Olivier Faynot, CEA-LETI
iv) Designing with Partially Depleted SOI, Jean-Luc Pelloie, SOISIC

For additional information, please contact:
2002 SOI Short Course Chair

AMD Inc 
One AMD Place 
PO Box 3453, MS 365 
Sunnyvale, CA  94088  
408/774-7835

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