GENERAL CHAIR
DR. DIMITRIS E. IOANNOU received his BSc (1974) degree in physics from the University of Thessaloniki, Greece and his MS (1975) and PhD (1978) degrees in solid-state electronics from the University of Manchester Institute of Science and Technology (UMIST), Manchester, England. He held positions with the Democritus University of Thace (Greece) and the University of Maryland (College Park) prior to his current position of profes-sor of electrical and computer engineering at George Mason University (Fairfax, VA). His main contributions include the development of SEM-EBIC techniques, SiC Schottky and Ohmic contact technology, and with regard to SOI technology, he developed techniques for the study of deep traps, carrier generation lifetime, and interface states. He also did research on device physics and hot carrier reliability of SOI devices. His research interests remain in devices and materials for VLSI. 

TECHNICAL PROGRAM CHAIR
DR. MICHAEL S. T. LIU received his PhD in electrical engineering from the University of Minnesota in 1967. He has been with Honeywell since 1968 and is currently a chief engineering fellow. He has contributed many techniques to harden the buried oxide of SOI substrates to meet ASIC and SRAM operation in extreme harsh radiation environment. He has been granted 18 U.S. patents and one Canadian patent. He was active in the IEEE Ferroelectric Committee in 1970 and 1980, and served as the general chairman of the 4th IEEE International Symposium on Applications of Ferroelectrics in 1979. He has authored or co-authored three chapters on pyroelectric coefficients, and more than 100 papers published in technical journals and conference proceedings in the areas of noise, ferroelectrics and pyroelectric detectors, selective epitaxy, and SOI materials and devices. His areas of current interest are SOI materials, deep submicron SOI CMOS devices and technology, and radiation hardening of SOI CMOS devices. 

LOCAL ARRANGEMENTS CHAIR
MIKE MENDICINO received his BS degree from Ohio State University in 1989, and his MS and PhD degrees in chemical engineering from the University of Illinois in 1994. He completed a two-year assignment at SEMATECH where he was a project leader responsible for thin film SOI materials characterization and development. He is currently with Motorola’s Digital DNA Laboratories working on advanced device technologies for high performance CMOS applications. Mike is a member of the technical staff at Motorola and member of IEEE. 

TREASURER & REGISTRATION CHAIR
DR. JAMES BURNS received the B.S. degree in physics from the Carnegie Institute of Technology in 1960 and the Ph.D. degree in physics from the University of Vermont in 1975. He worked in semiconductor and magnetic film device design and processing at IBM and CCD design while at Honeywell.  Since 1975 has been a staff member at MIT's Lincoln Laboratory where his principal interests are silicon transistor and process design and the development of analytical techniques to customize IC fabrication to integrated circuit applications. He developed the laboratory's  deep sub-micron fully depleted SOI process and is currently working on integrating that SOI technology into a three-dimensional integrated circuit technology. He is a member of the American Physical Society, IEEE, and Tau Beta Pi.

SHORT COURSE CHAIR
DR. CHRISTOPHE TRETZ received his BSc degree (1991) from the Ecole Nationale Superieure d'Electronique, Electrotechnique, Informatique et Hydraulique de Toulouse (ENSEEIHT), France, and his MS (1992) and PhD in Electrical Engineering (1997) from Columbia University, New York. He joined IBM at the TJ Watson Research Center in Yorktown Heights, NY in 1997 and contributed to the design of several microprocessors for servers and workstations both with bulk and SOI processes. In 2000, he joined Advanced Micro Devices, in the California Microprocessor Division, as a member of the technical staff, and he is contributing to the design of the Hammer microprocessor family, and is establishing design guidelines for microprocessor using SOI technologies. Dr. Tretz has authored or coauthored about 20 papers and 3 US patents in the field of circuit design techniques using SOI, circuit optimization and low power design. His current research interests remain in optimizing circuit design for SOI and in improving design choices for SOI.

RUMP AND POSTER CHAIR
DR. OLIVIER FAYNOT received the M.Sc and Ph.D. degrees from the Institut National Polytechnique de Grenoble, France in 1991 and 1995, respectively. His doctoral research was related to the characterization and modeling of deep submicron Fully Depleted SOI devices fabricated on ultrathin SIMOX wafers. From 1995 to 2000, he has been with LETI/CEA, Grenoble, working on simulation and modeling of deep submicron fully and partially depleted SOI devices. His main activity was the development of a dedicated Partially Depleted SOI model, called LETISOI. Since 2000, he is involved in the development of a sub 0.1µm partially depleted technology. He is author and co-author of more than 20 scientific publications on SOI in journals and international conferences.
 
 

PUBLICITY CHAIR
See above for DR TRETZ information.