Rump and Poster Chair

LEG Laboratory

Swiss Federal Inst. of Technology

CH-1015 Lausanne, Switzerland

+41-21-6934604

University of Tokyo

4-6-1 Komaba, Meguro-ku

Tokyo 153-8505, Japan

+81-3-5452-6263

Publicity Chair

IBM Research Division

TJ  Watson Research Center

RT 134 Ketchwan Rd.

Yorktown Heights, NY 10598

(914) 945-1118

GENERAL CHAIR
DR. LIU earned his Ph. D degree in Electrical Engineering at the University of Minnesota in 1967.  He has been with Honeywell since 1968 and is currently a chief engineering fellow at Solid State Electronics. He did research and development for Honeywell on ferroelectric materials for pyroelectric infrared detectors from 1969 to 1979. He served as the general chairman of the 4th IEEE International Symposium on Applications of Ferroelectrics in 1979. Between 1978-1984, he worked on Honeywell's submicron technology development.  Between 1985 and 1989 he worked on a collaborative research program with Purdue University on Epitaxial Lateral Overgrowth (ELO).  Since 1990, he has been developing radiation hardening techniques for SIMOX and UNIBOND^TM substrates so that ASIC and SRAM fabricated in them can function properly in harsh radiation environments. His current interest is on SOI materials, total dose hard and single event hard deep submicron SOI devices.  He has authored and co-authored over 100 journal and conference papers and has eighteen patents.

TECHNICAL PROGRAM CHAIR
MIKE MENDICINO received his BS degree from Ohio State University in 1989, and his MS and PhD degrees in chemical engineering from the University of Illinois in 1994. He completed a two-year assignment at SEMATECH where he was a project leader responsible for thin film SOI materials characterization and development. He is currently with Motorola’s Digital DNA Laboratories working on advanced device technologies for high performance CMOS applications. Mike is a member of the technical staff at Motorola and member of IEEE. 

LOCAL ARRANGEMENTS CHAIR
DR. JAMES BURNS received the B.S. degree in physics from the Carnegie Institute of Technology in 1960 and the Ph.D. degree in physics from the University of Vermont in 1975. He worked in semiconductor and magnetic film device design and processing at IBM and CCD design while at Honeywell.  Since 1975 has been a staff member at MIT's Lincoln Laboratory where his principal interests are silicon transistor and process design and the development of analytical techniques to customize IC fabrication to integrated circuit applications. He developed the laboratory's  deep sub-micron fully depleted SOI process and is currently working on integrating that SOI technology into a three-dimensional integrated circuit technology. He is a member of the American Physical Society, IEEE, and Tau Beta Pi.

TREASURER & REGISTRATION CHAIR
DR. CHRISTOPHE TRETZ received his BSc degree (1991) from the Ecole Nationale Superieure d'Electronique, Electrotechnique, Informatique et Hydraulique de Toulouse (ENSEEIHT), France, and his MS (1992) and PhD in Electrical Engineering (1997) from Columbia University, New York. He joined IBM at the TJ Watson Research Center in Yorktown Heights, NY in 1997 and contributed to the design of several microprocessors for servers and workstations both with bulk and SOI processes. In 2000, he joined Advanced Micro Devices, in the California Microprocessor Division, as a member of the technical staff, and he is contributing to the design of the Hammer microprocessor family, and is establishing design guidelines for microprocessor using SOI technologies. Dr. Tretz has authored or coauthored about 20 papers and 3 US patents in the field of circuit design techniques using SOI, circuit optimization and low power design. His current research interests remain in optimizing circuit design for SOI and in improving design choices for SOI.

SHORT COURSE CHAIR
DR. TOSHIRO HIRAMOTO Toshiro Hiramoto received B.S., M.S., and Ph.D degrees in electronic engineering from the University of Tokyo in 1984, 1986, and 1989, respectively. In 1989, he joined Device Development Center, Hitachi Ltd., Ome, Japan, where he was engaged in the device and circuit design of ultra-fast BiCMOS SRAMs. In 1994, he joined Institute of Industrial Science, University of Tokyo, Japan, as an Associate Professor. He was also an Associate Professor in VLSI Design and Education Center, University of Tokyo, from 1996 to 2002. He has been a Professor in Institute of Industrial Science, University of Tokyo since 2002. His research interests include low power and low voltage design of advanced CMOS devices, SOI MOSFETs, device/circuit cooperation scheme for low power VLSI, quantum effects in nano-scale MOSFETs, and silicon single electron transistors. Dr. Hiramoto is a member of IEEE, IEICE, and Japan Society of Applied Physics. He has been an Elected AdCom Member of IEEE Electron Devices Society since 2001. He served as the Program Chair of Silicon Nanoelectronics Workshop in 1997, 1999, and 2001.

RUMP AND POSTER CHAIR
DR. PIERRE FAZAN was born in Lausanne, Switzerland where he obtained his Physics diploma and Ph.D degrees at the Swiss Federal Institute of Technology (EPFL) in 1984 and 1988 respectively. From 1989 to 1997 he worked as process integration engineer then manager at Micron Technology, Boise USA, focusing on DRAM process integration. In 1997 he was named Professor at the Swiss Federal Institute of Technology, Lausanne, EPFL. In 1999 he founded Innovative Silicon Solutions, a consulting company specialized in embedded memory design and integration. In 2002 he co-founded Innovative Silicon S.A., an IP startup developing a new SOI single transistor memory concept. He authored or co-authored more than 95 papers and invented or co-invented more than 140 US patents. Dr. Fazan has served as member in program committees of IEDM, VLSI Tech. Symp, ISIF, ESSDERC, INFOS and ECS Conferences.
 

PUBLICITY CHAIR
  Dr. Rajiv V. Joshi is a research staff member at T. J. Watson research center, IBM. He received his B.Tech degree from Indian Institute of Technology (Bombay, India), M.S degree from Massachusettes Institute of Technology and Doctorate in Eng. Science from Columbia University, USA. From 1981 to 1983, he with GTE research lab in Waltham, Massachusettes. He joined IBM in Nov. 1983, and since then is working in VLSI design systems, science and technology. He worked on 1.25mm NMOS, and CMOS, sub-0.5mm CMOS logic, DRAM and SRAM technologies. He developed novel interconnect processes and structures for Aluminum, tungsten and Copper technologies which are widely used in IBM for various sub-0.5mm memory and logic technologies as well as across the globe. His circuit related work includes design of register files, registers, latches, L1 caches, Directory, TLB, IO circuits development of physical design tools, and CAD based library generation and circuit designs in SOI technology. He contributed to S/390 Alliance processor design, working in both circuit design and CAD tools. His 2 GHz SRAM design for System 390 servers received Outstanding technical achievement award. He has won twenty-six invention plateau achievement awards from IBM and won two patent portfolio awards for cross-licensing and utilization of his patents in the IBM products. He has received 5 Research Division Awards, and several top 5% and top 30% patent awards (for licensing activities) and a Corporate Patent Portfolio award from IBM. He is a master inventor & key technical leader at IBM research division. He has authored and co-authored over 95 research papers and presented several invited talks. He holds 60 U.S. patents in addition to 40 pending patents. He received the Lewis Winner Award in 1992 for an outstanding paper he coauthored at the International Solid State Circuit Conference. He was instrumental in starting interconnect workshop in early 1980s. He chaired advanced interconnect conferences sponsored by MRS and served as an editor of the proceedings. He is elected as an IEEE fellow for 2002 for contributions to chip metallurgy materials and processes, and high performance processor and circuit design. He is actively involved in IEEE ISLPED (Int. Symposium Low Power Electr. Design) IEEE VLSI design, IEEE Int. SOI conf Program committees.

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