2001 SOI Advance Program

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The technical program will consist of 43 oral and 17 poster papers, as well as three invited talks. 
The Technical Session and Session Chairs are as follows:


MONDAY, October 1
Short Course
Welcome Reception

TUESDAY, October 2
7:00am Registration, Continental Breakfast
8:00am Introduction & Welcome

Chair: Dimitris Ioannou
8:15am 1.1 Advantages and Challenges of High Performance Logic on SOI Mario M. Pelella
8:55am 1.2 Technology and Status of SOI Materials Lisa Allen
9:35am 1.3 Nano-Scale Silicon MOSFET: Towards Non-Traditional and Quantum Devices Toshiro Hiramoto
10:15am Break

Chair: Maria Anc/George Celler
10:40am 2.1 Atomic-layer Cleaving with Six Gey Strain Layers for Fabrication of Si and Ge-rich SOI Device Layers M.I. Current, S.N. Farrens, M. Fuerfanger, S. Kang, H.R. Kirk, I.J. Malik, L. Feng, F.J. Henley; Silicon Genesis
11:00am 2.2 SiGe-On-Insulator (SGOI): Substrate Preparation and MOSFET Fabrication for Electron Mobility Evaluation Z-Y Cheng, M.T. Currie, C.W. Leitz, G. Taraschi, A. Pitera, M.L. Lee, T.A. Langdo, J.L. Hoyt, D.A. Antoniadis and E.A. Fitzgerald; Massachusetts Institute of Technology
11:20am 2.3 BOX Layer Formation by Oxygen Precipitation at Implantation Damage of Light Ions A. Ogura; NEC Corporation
11:40am 2.4 Application of Laser Scattering and Optical Defect Detection Methods to SIMOX-SOI Wafers M. Alles, J. Dunne, C. Treadwell, B. Fiordalice, R. Nguyen Ibis Technology Corp., KLA-Tencor Corp.; AMD
12:00pm 2.5 Defect Detection on SOI Wafers Using Laser Scattering Tools C. Maleville, E. Neyret, L. Ecarnot, T. Barge and A.J. Auberton; SOITEC S.A.
12:20pm Lunch

Chair: James Burns/Srinath Krishnan
1:30pm 3.1 Design Analysis of Thin-Body Silicide Source/Drain Devices J. Kedzierski1, M. Ieong, P. Xuan, J. Bokor, T-J King, and C. Hu University of California Berkeley, IBM
1:50pm 3.2 0.11µm Fully-Depleted SOI CMOS Devices with 26nm Silicon Layer Fabricated by Bulk Compatible Process H. Komatsu, H. Nakayama, K. Koyama, K. Matsumoto, T. Ohno and K. Takeshita; Sony Corporation
2:10pm 3.3 Explaining the Reduced Floating Body Effects in Narrow Channel SOI MOSFETs J. Pretet, N. Subba, D. Ioannou, S. Christoloveanu, W. Maszara, and C. Raynaud LPCS (UMR CNRS&INPG, George Mason University, STMicroelectronics, AMD, LETI, CEA
2:30pm 3.4 fT Variation Caused by Channel Width Effects in Ladder Gate Structure for RF SOI MOSFETs H. Lee, J-H Lee, Y.J. Park, and H.S. Min Seoul National University,
School of Electrical Engineering
2:50pm 3.5 Exploitation of Volume Inversion in Optimal DG MOSFET Design L. Ge and J.G. Fossum; University of Florida
3:10pm 3.6 Self-Heating Enhanced Impact Ionization in SOI MOSFETs P. Su, K.Goto,
T. Sugii, and C. Hu University of California Berkeley; Fujitsu Laboratory Ltd.

3:30pm Chair: John Conley
P1 Comparison of Boron Diffusion Profiles in Ultra Thin SOI Structures H. Uchida, M. Ichimura and E. Arai; Nagoya Institute of Technology & Computer Engineering
P2 Gas Cluster Ion Beam Processing of SOI Surfaces for Improved Gate Oxide Integrity
L.P. Allen, J. Hautala, C. Santeufemio, W. Brooks, D.B. Fenner, T. Lucking, M. Liu
Epion Corporation, Honeywell SSEC
P3 Characterization of SOI Wafers by Temporal Decay Measurement of Condensate
Luminescence S. Ibuka and M. Tajima; Institute of Space and Astronautical Science
P4 FTIR Dosimetry Mapping of as-Implanted SIMOX Wafers V.A. Yakovlev, P.A. Rosenthal, and M.J. Anc; MKS Instruments, Inc., Ibis Technologies Corp.
P5 New Implant Equipment for the Production of Commercial SOI Substrates
N.R. White, M. Sieradzki, and E.W. Bell; Diamond Semiconductor Group, LLC
P6 Effect of Implant Dose and Energy on Formation of Thin SOI Structure in SIMOX Using Water Plasma J. Chen, M. Chen, X. Wang, Y. Dong, Z. Zheng, and X. Wang; Chinese Academy of Sciences
P7 Ultra-Thin Film Fully-Depleted SOI CMOS with Raised G/S/D Device Architecture for
Sub-100nm Applications H. van Meer and K. De Meyer; IMEC
P8 Recessed Multi-Gate SOI MOSFET in Deep Decanonometer Regime J-T Lin, S-C Chang, K-Y Huang, Y-Y Xu, P-S Jue; NSYSU
P9 Simulations of Ultrathin SOI with Quantum Transport Models E. Lyumkis, R. Mickevicius, O. Penzin, B. Polsky, K. El Sayed, and A. Wettstein; Integrated Systems Engineering, Inc.
P10 Phenomenalistic Reconsideration of Hooge Parameter in Buried-Channel
Metal-Oxide-Semiconductor Field-Effect Transistors Y. Omura; Kansai University
P11 Threshold Voltage Fluctuation Analysis in Dynamic Threshold MOSFET Based on
Charge-Sharing M. Terauchi; Hiroshima City University
P12 80nm SOI CMOS Parameter Extraction for BSIMPD K. Goto, P. Su, Y. Tagawa,
T. Sugii, C. Hu; University of California Berkeley, Fujitsu Labs
P13 Measurement of History Effect in PD/SOI Single-Ended CPL Circuit K.A. Jenkins, R. Puri, C.T. Chuang, and F.L. Pesavento; IBM Corporation
P14 Multiple Output Domino Logic (MODL) in SOI R. Kanj and E. Rosenbaum; University of Illinois
P15 Implementation of a Multi-Bit Då A/DC Without a Correction RAM C-M Liu, S.G. Lim, C. Hutchens, I. Lagnado; Oklahoma State University
P16 Novel 0.8V True-Single-Phase-Clocking (TSPC) Latches Using PD-SOI DTMOS Techniques for Low-Voltage CMOS VLSI Circuits J.B. Kuo and T-Y Chiang University of Waterloo, NTUEE
P17 5+ GHz CMOS Prescaler F. Lam and G. Wu; Peregrine Semiconductor Corp.

6:30pm Banquet Reception
7:00pm Banquet

WEDNESDAY, October 3
7:00am Continental Breakfast
Chair: Michael Mendicino/Michio Tajima
8:00am 5.1 A Novel Shallow Trench Isolation Technology Using LPCVD MTO/SiN Liner in SOI Wafer T.J. Lee, D. Park, Y.H. Roh, B.S. Kim, D.H. Ahn, E.H. Kim, C.H. Jeon, Y. W. Kim, S.C. Lee, C.S. Choi, K.P. Suh; Samsung Electronics Co., Sungkyunkwan University
8:20am 5.2 Reduction of STI/active Stress on 0.18µm SOI Devices Through Modification of STI Process W.G. En, D-H Ju, D. Chan, S. Chan, and O. Karlsson; AMD
8:40am 5.3 Characterization and Simulation of STI Isolation for 0.1µm Partially-Depleted SOI Devices C. Fenouillet-Beranger, , O. Faynot, C. Tabone, T. Colladant, V. Ferlet, , C. Jahan, J. duPort de Pontcharra, G. Lecarval, J.L. Pelloie; LETI/CEA, DAM/CEA
9:00am 5.4 Ar Implantation Effects in SOI NMOSFETs Under Low Voltage Operation
T. Shino, H. Nii, S. Kawanaka, K. Inoh, Y. Katsumata, M. Yoshimi, and H. Ishiuchi;
Toshiba Corp.
9:20am 5.5 Metal Gates for Advanced Sub-80-nm SOI CMOS Technology B. Cheng, B. Maiti, S. Samavedam, J. Grant, B. Taylor, P. Tobin, and J. Mogab; Motorola
9:40am 5.6 Double-Gate SOI MOSFET Fabrication from Bulk Silicon Wafer X. Lin, G. Feng, S. Zhang, W-H Ho, M. Chan; Hong Kong University of Science & Technology
10:00am Break

Chair: Theodore Houston/Christophe Tretz
10:25am 6.1 A Low-Cell-Stress SOI SRAM Sensing Technique J.B. Kuang, A.G. Aipperspach, T.A. Christensen, and F. Assaderaghi; IBM Corp. Advanced Server Development, IBM Corp. T.J. Watson Research Center
10:45am 6.2 0.15um SOI DRAM Technology Incorporating Sub-Volt Dynamic Threshold Devices for Embedded Mixed-Signal & RF Circuits D. Goldman, K. DeGregorio, C.S. Kim, M. Nielson, J. Zahurak, and S.Parke; Boise State University, Micron Technology, Inc.
11:05am 6.3 Novel Circuits to Improve SRAM Performance in PD/SOI Technology
R.V. Joshi, A. Bhavnagarwala, L.L. Hsu, C.T. Chuang, W. Hwang; I BM Research Division,
IBM Microelectronic Division
11:25am 6.4 Assessing Circuit Level Impact of Self-Heating in 0.13µm SOI CMOS
S.P. Sinha, M. Pelella, C. Tretz, and C. Riccobene; AMD
11:45am 6.5 Circuit Style Comparison Based on the Variable Voltage Transfer Characteristic and Floating ß Ratio Concept of Partially Depleted SOI K.K. Das and R. Brown; University of Michigan
12:05pm 6.6 Layout Optimization of Cascode RF SOI Transistors M. Marenk, E. Ristolainen; Tampere University of Technology
12:25pm 6.7 New Substrate-Crosstalk Reduction Structure Using SOI Substrate
Y. Hiraoka, S. Matsumoto, and T. Sakai; NTT Telecommunications Laboratories

12:45pm Lunch & Activities
6:30pm “Cook-out” Dinne r
8:00pm Rump Session

THURSDAY, October 4
7:00am Continental Breakfast

Chair: Jason Woo/Toshiro Hiramoto
8:00am 7.1 Lateral Gate-All-Around (GAA) poly-Si Transistors P. Kalavade and K.C. Saraswat; Stanford University
8:20am 7.2 Quasi-Planar FinFETs with Selectively Grown Germanium Raised  Source/Drain N. Lindert, Y-K Choi, L. Chang, E. Anderson, W-C Lee, T-J King, J. Bokor,
C. Hu; University of California Berkeley, Lawrence Berkeley National Laboratory, Intel Corporation
8:40am 7.3 Characterization of Fully Depleted SOI Transistors after Removal of the Silicon Substrate J. Burns, K. Warner, and P. Gouker; Massachusetts Institute of Technology
9:00am 7.4 Comparison of Gate Structures for Short-Channel SOI MOSFETs J.T. Park,
C.A. Colinge, and J.P. Colinge; University of Inchon, Cal State University Sacramento,
University of California Davis
9:20am 7.5 Multi-Layers with Buried Structures (MLBS):An Approach to Three-Dimensional Integration L. Xue, C.C. Liu, and S. Tiwari; Cornell University
9:40am 7.6 Single-Mode Silicon Optical Switch with T-shape SiO2 Waveguide as a Control Y. Iida, Y. Omura, and H. Kobayashi; Kansai University

10:00am Break

Chair: Michael Liu/John Conley
10:20am 8.1 Worst Case Conditions for Hot-Carrier Induced Degradation of Sub-100nm Partially Depleted SOI MOSFETs E-X Zhao, S.P. Sinha, and D-H Ju; AMD
10:40am 8.2 The Role of Externally Applied Body-Bias on the Hot-Carrier Degradation of Partially Depleted SOI N-MOSFETs F. Dieudonne, J. Jomaah, D. Ioannou, C. Raynaud,
and F. Balestra; Laboratorie de Physiques des Composants Semiconducteurs, George Mason University, CEA/Leti
11:00am 8.3 Radiation Induced Degradation of SOI n-channel LDMOSFETs J.F. Conley, Jr., A. Vandooren, L. Reiner, S. Cristoloveanu, M. Mojarradi, and E. Kolowa; JPL, 
Motorola, California State University Nothridge, LPCS/ENSERG
11:20am 8.4 Modeling the Gated-Diode Response of an Irradiated SOI Back-Channel Interface R.K. Lawrence, A.A. Salman, D.E. Ioannou, W.C. Jenkins, and S.T. Liu; SFA Inc., George Mason University, Naval Research Laboratory, Honeywell
11:40am 8.5 Study of Relevance of the SIMOX Defect Type on Yield of Radiation-Tolerant Device Test Structures M.J. Anc, L.P. Allen, M.L. Alles, R.P. Dolan, S.T. Liu, J.G. Sullwold,
M. Gostein, M. Banet; Ibis Technology Corp., Honeywell, Phillips Analytical
12:00pm 8.6 Evaluating Manufacturability of Radiation-Hardened SOI Substrates
M. Alles, B. Dolan, H. Hughes, P. McMarr, P. Gouker, M. Liu; Ibis Technology Corp., 
Naval Research Laboratory, Lincoln Laboratory MIT, Honeywell

12:20pm Lunch

Chair: Rajiv Joshi/Olivier Faynot
1:30pm 9.1 Comparison of Bulk vs SOI for Low Power Low Voltage CMOS Imager
A. Afzalian, P. Delatte, J-D Legat, and D. Flandre; Universite catholique de Louvain

1:50pm 9.2 A Tri-State Body Charge Modulated SOI Sense Amplifier J.B. Kuang and C.T. Chuang; IBM Corp. Advanced Server Development, IBM Corp. T.J.Watson Research Center Ltd.
2:10pm 9.3 A Novel CMOS SOI Unbalanced Mach-Zehnder Interferometer: from Design and Simulations to Fabrication and Characterization P. Dainesi, L. Thevenaz, Ph. Fluckiger, C. Hibert, G. Racine, Ph. Robert, Ph. Renaud, A.M. Ionescu, and M. Declercq;
Swiss Federal Institute of Technology
2:30pm 9.4 Design of a SOI Fully Integrated 1V, 2.5GHz Front-end Receiver C. Tinella, J.M. Fournier; LEMO UMR 5530 INPG-CNRS-UJF
2:50pm 9.5 Characteristics of RF Power Amplifiers by 0.5µm SOS CMOS Process
S. Lam, W-H Ki, and M. Chan; Hong Kong University of Science & Technology
3:10pm 9.6 A 0.5-1V MTCMOS/SIMOX ROM Macro with Low-Vth Memory Cells 
T. Douseki, N. Shibata, and J. Yamada; NTT Telecommunications Energy Laboratories
NTT Electronics Corporation

3:30pm Break

3:50pm Chair: Harry Hovel

4:50pm Wrap-up & Presentation of Best Paper Award


Late News papers will be accepted until August 15, 2001 and presented on Thursday afternoon of the conference.
Authors will be available for questions Tuesday, October 2nd, 3:30pm to 5:30pm.
Posters will be on display from Tuesday, 3:30pm until Thursday, 12:00pm.
Several companies have recently begun manufacturing products on SOI. Despite increasing mainstream acceptance, SOI design is not yet routine and there are still many peculiarities with which circuit designers must contend such as floating body, self heating,
history dependence, etc. What is the status of TCAD tools for SOI circuit design? What tools are available to assist the designer? What improvements are needed? Finally, once an SOI circuit is successfully designed, what are the options for getting it built on
SOI? What is status of SOI foundries? How difficult is it to get an SOI design built? A panel of experts will discuss these issues.
Tuesday 4:00pm - 7:00pm
(includes pre-dinner reception)
Wednesday 8:00am - 12:00pm
Thursday 8:00am - 12:00pm
Confirmed exhibitors as of July 15th:
Hitachi America, Ltd.
Integrated System Engineering, Inc.
Peregrine Semiconductor Corp.
Silicon Genesis Corp.

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