38th Annual Conference • Napa, California
The Meritage Resort and Spa
Ever increasing demand and advances in SOI and related technologies make it essential to meet and discuss new gains and accomplishments in the field. For over 35 years the IEEE International SOI Conference has been the premier meeting of engineers and scientists dedicated to current trends in Silicon-on-Insulator technology. Sponsored by the IEEE Electron Devices Society,the conference traditionally provides a forum for open discussion in all areas of SOI technologies and applications as well as the introduction of new developments presented in original papers presented at the technical sessions.
AREAS OF FOCUS
• SOI DEVICE PHYSICS AND MODELING
• SUBSTRATE ENGINEERING
(IV and III-V advanced substrates, hybrid Si and III-V integration, GaN on Si)
• NEW DEVICES/PHYSICS USING ADVANCED SUBSTRATES
(III-V & IV CMOS, hybrid SI, Beyond CMOS, heterojunctions, graphene, nanowires, etc.)
• FULLY-DEPLETED/THIN-BODY DEVICES
(BULK & SOI FinFET, multi-gate, tunnel FET, others)
• HIGH-VOLTAGE DEVICES
(SOI, GaN,SiC, IGBT, HEMT, new devices)
• MANUFACTURABILITY AND PROCESS INTEGRATION OF SOI & FULLY- DEPLETED DEVICES
• LOW-POWER/LOW-VDD/SUB-VT SOI & FULLY-DEPLETED TECHNOLOGY AND CIRCUIT DESIGN INFRASTRUCTURE
• SOI CIRCUIT APPLICATIONS
(high-performance & low-power MPU, SRAM, ASIC, hith-voltage, RF, analog, mixed
mode, FPGA, etc.))
• NEW SOI STRUCTURES, CIRCUITS, AND APPLICATIONS
(displays, microactuators, novel memories, optics, etc.)
• SOI RELIABILITY ISSUES
(hot-carrier effects, radiation effects, high-temperature effects, NBTI/PBTI, etc.)
• SOI SENSORS, NEMS, MEMS, AND RFID TECHNOLOGY AND
APPLICATIONS
• 3D INTEGRATIONS
(imagers, power devices, wafer-to-wafer and die-to-wafer 3D integration)
• SOI PHOTONICS